Advances in surface mount technology and printed circuit board (PCB) manufacture have resulted in more complex and smaller PCBs that have higher integrated circuit (IC) density. Surface mount devices (SMDs) and very large-scale integrated (VLSI) circuits often have minimal spacing between pins and some PCBs include SMDs mounted to both sides, which further increases board complexity. Contact test methods for such devices (in which the test fixture directly contacts the pins or other electrical contacts on a PCB) have become correspondingly more complex and costly. In order to test devices with higher pin pitches, test fixtures utilize ever smaller probe tips or alternative electrical contact apparatus, and similarly, testing of devices having ICs mounted on both sides of a PCB can require substantial modification of pre-existing test fixtures.
In 1990, the Institute of Electrical and Electronic Engineers (IEEE) adopted a standard for a non-contact method of testing PCBs named the IEEE Standard Test Access Port and Boundary Scan Architecture. The standard, designated IEEE 1149.1, is also commonly referred to as the Joint Test Action Group (JTAG) standard or just JTAG. JTAG logic can be incorporated into an IC that implements test methods including in-circuit testing of an IC itself, testing of connections between ICs in an assembled PCB, and operational testing for observing and modifying circuit activity during normal operation. The test logic permits software control and observation of boundary scan cells. Boundary scan cells are cells located adjacent to respective IC pins that permit signals at the IC boundaries to be controlled and observed, and each boundary scan cell can include a shift register stage. The boundary scan cells permit test data to be placed at an output and/or input pin of an IC without the need for a physical probe. The boundary scan cells of an IC can be interconnected to form a shift register chain that can include serial input and output connections and clock and control signals. Test data can be shifted serially into and out of boundary scan registers connected to a bus within the IC. The boundary scan bus can be accessed through a Test Access Port (TAP).
Conventionally, the TAP controls an interface between the boundary scan registers on the IC and a boundary scan bus. The TAP can be, for example, a state machine controlling the operations associated with the boundary scan cells. A conventional TAP controller interface is based on four ports. The Test Clock (TCK), Test Mode Select (TMS), Test Data In (TDI), and Test Data Out (TDO) ports of a TAP controller can be used to control the basic operation of the TAP. The TCK and TMS ports can direct signals between TAP controller states. The TDI and TDO ports can receive the data input and output values serially from the boundary scan registers. An optional fifth port, Test Reset (TRST), can be implemented as an asynchronous reset signal to the TAP controller.
A JTAG device (e.g., an external test device) can communicate with a TAP controller using a JTAG serial protocol for full duplex serial synchronous communication with the TAP controller. A JTAG master that forms part of the JTAG device, and a JTAG TAP controller can include logic for accessing the internal memory in a microcontroller.